The present invention relates to semiconductor device manufacturing technology.
In connection with semiconductor devices of the type incorporated in small size electronic equipment, such as mobile phones, personal digital assistants and mobile personal computers, there is a demand for thin models, compact models and multi-pin models. As an example of semiconductor devices which meet such a demand, CSP (Chip Size Package) type devices are known. Various types of CSP type semiconductor devices have been proposed and commercialized. One of them is a CSP type semiconductor device which is manufactured using wafer packaging technology which combines wafer processing and a package assembly process (hereinafter called a wafer level CSP type semiconductor device). It is easier to make the wafer level CSP type semiconductor device into a compact, low cost model than what is called the chip level CSP type semiconductor device (CSP type semiconductor device which is manufactured by packaging, one by one, semiconductor chips produced by segmenting a semiconductor wafer), because the package flat surface size of the wafer level CSP type semiconductor device is almost equal to the semiconductor chip flat surface size.
The wafer level CSP type semiconductor device mainly includes: a chip layer which corresponds to a semiconductor chip; a rewiring (secondary wiring) layer formed over the main surface of the chip layer; and solder bumps (protruding electrodes) disposed as external connection terminals over the secondary wiring layer. The chip layer includes: a semiconductor substrate; a multilayer wiring layer (primary wiring layer) formed as a laminate of plural insulating layers and plural wiring layers; and a surface protective film which covers the multilayer wiring layer. In the chip layer, electrode pads (bonding pads) are formed over the top wiring layer of the primary wiring layer, and the surface protective film has bonding holes which expose the electrode pads.
The secondary wiring layer is a layer (interposer) designed to arrange electrode pads with larger pitches than electrode pads in the primary wiring layer in order to match the pitches of electrode pads of a wiring board where a semiconductor device is mounted (mounting board). The electrode pads in the secondary wiring layer are electrically connected with the electrode pads in the primary wiring layer. Solder bumps are electrically and mechanically connected with the electrode pads in the secondary wiring layer.
An example of a wafer level CSP type semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 2002-305285 (Patent Literature 1).